PrePrint: Integrated Systems In The More-Than-Moore Era: Designing Low-Cost...
Moore’s law has provided a metronome for semiconductor technology over the past four decades. However, when CMOS transistor feature size and interconnect dimensions approach their fundamental limits,...
View ArticlePrePrint: Hardware IP Protection During Evaluation Using Embedded Sequential...
Evaluation of hardware Intellectual Property (IP) cores is an important step in an IP-based system-on-chip (SoC) design flow. From the perspective of both IP vendors and Integrated Circuit (IC)...
View ArticlePrePrint: xMAS: Quick Formal Modeling of Communication Fabrics to Enable...
Although communication fabrics at the microarchitectural level are mainly composed of standard primitives such as queues and arbiters, to get an executable model one has to connect these primitives...
View ArticlePrePrint: Scan-based Speed-path Debug for a Microprocessor
Speed-path debug is a critical step in improving clock frequency of a design to meet the performance requirement. However, speed-path debug based on functional patterns can be very expensive. In this...
View ArticlePrePrint: Handling Nondeterminism in Logic Simulation So That Your Waveform...
The increasing complexity of integrated circuits pushes for more aggressive design optimizations, such as resetting only part of design registers, that can leave some registers in nondeterministic (X)...
View ArticlePrePrint: Organizational Dynamics: Understanding the Impact of Organizational...
Modern complex ULSI designs require significant investment of engineering resources for successful execution. At the same time, competing requirements for low cost design and faster time to market will...
View ArticlePrePrint: Dual-Control Self-Healing Architecture for High Performance Radio...
This paper presents a self-healing architecture and algorithms that enable a transceiver to heal itself of impairments caused by process variations, which has become increasingly severe in deep...
View ArticlePrePrint: Expedited-Compact Architecture for Average Scan Power Reduction
Excessive switching activity during scan operations endangers the reliability of the chip under test. We propose an architectural solution, which we refer to as Expedited-Compact, to mitigate the scan...
View ArticlePrePrint: Digitally Intensive Receiver Design: Opportunities and Challenges
Digitally enhanced wireless receivers are gaining prominence due to their promise of greater integration, flexibility to adapt to varying SNR conditions, performance and area benefit that comes with...
View ArticlePrePrint: Dynamic Specification Testing and Diagnosis of High Precision...
Testing dynamic specifications, THD (total-harmonic-distortion), SNR(signal-to-noise ratio) and ENOB (effective-number-of-bits), of high-resolution sigma-delta (ÄÓ) converters is extremely challenging...
View ArticlePrePrint: A New Approach for Automatic Test Pattern Generation in Register...
In this paper, we propose an approach to generate high-level test patterns from the arithmetic model of an RTL circuit using a hybrid canonical data structure based on a decision diagram. High-level...
View ArticlePrePrint: LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift...
Moving further into the deep-submicron era, the problem of test-induced yield loss due to high power consumption has increasingly worsened. One of the major causes of this problem is shift timing...
View ArticlePrePrint: Design Methods for Parallel Hardware Implementation of Multimedia...
Traditionally, parallel implementations of multimedia algorithms are carried out manually, since the automation of this task is very difficult due to the complex dependencies that generally exist...
View ArticlePrePrint: Advances in Parallel Discrete Event Simulation for Electronic...
At the Electronic System Level (ESL), design validation often relies on discrete event simulation. Recently, Parallel Discrete Event Simulation (PDES) for ESL models has gained attention again as it...
View ArticlePrePrint: Multicore Algorithms for Transient Noise Simulation
Accurate simulation of analog and mixed-signal circuit designs prior to fabrication is a necessity to confirm that adequate performance is achieved over process, voltage, and environmental variations....
View ArticlePrePrint: Time is money
The well-known saying, 'time is money,' is nowhere more true than in the world of electronics. As the pace of this industry continues to increase, seemingly with each new semiconductor process node,...
View ArticlePrePrint: Dispelling the Myths of Parallel Computing
As serial computing performance gains have diminished, there has been a resurgence of interest in parallel computation. For some problems, parallel systems can achieve near linear performance gains;...
View ArticlePrePrint: Diverse Double Modular Redundancy: A New Direction for Soft Error...
Soft errors are becoming an important issue for deep submicron technologies. To protect circuits against soft errors, designers routinely introduce modular redundancy to detect and correct these...
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